Dr. Md. Anwarul Abedin

Professor, Department of EEE, Dhaka University of Engineering & Technology, Gazipur

Ph.D. in Very Large Scale Integration  (HU, Japan), M.Sc. Engg. &  B.Sc. Engg. (BUET, Bangladesh).

Office Address: Room # 224, Old Academic Building

PABX: 49274034-53  Extn: 3027 (Off) & 3028 (Res)

Phone: (+88) 01712070009

E-mail: abedin@duet.ac.bd Send Email

Alternate:

Phone: (+88) 

E-mail: abedin14@gmail.com

T&T: (+88) 

Other:

Per. Site:

Degree University Year Discipline
Post-Doctoral Bangladesh University of Engineering and Technology, Bangladesh 2015 ~ 2017 Very Large Scale Integration (VLSI)
Ph.D. Hiroshima University, Japan 2007 Very Large Scale Integration (VLSI)
M.Sc. Bangladesh University of Engineering and Technology, Bangladesh 2002 Solid State Electronics
B.Sc. Bangladesh University of Engineering and Technology, Bangladesh 1999 Electrical and Electronic Engineering
Undergraduate Courses
  • EEE-1103: Electrical Circuit-I
  • EEE-2301: Electrical Machines-I
  • EEE-2501: Electronics-I
  • EEE-3701: Electrical & Electronic Measurement
  • EEE-4701: Control System
  • EEE-4705: VLSI Circuits
  • EEE-4907: High Voltage Engineering
Post-Graduate Courses
  • EEE-6609: Digital Integrated Circuit Design
  • EEE-6705: MOS Devices
  • EEE-6706: Optoelectronic Devices
  • ICT-6605: Advanced VLSI Designand Testing
Name Topic
Field of Specialization Solid State Electronics, Mixed Digital-Analog VLSI
Research Interest Solid State Electronics, Mixed Digital-Analog VLSI , Industrial Electronics, PLC
Year & Duration Designation Scope of Works Company/Institute/University
October 10, 2011 ~ Present Professor, Dept. of EEE Teaching and Research Dhaka University of Engineering & Technology (DUET), Gazipur
November 16, 2009 ~ October 9, 2011 Associate Professor, Dept. of EEE Teaching and Research Dhaka University of Engineering & Technology (DUET), Gazipur
April 01, 2003 ~ November 15, 2009 Assistant Professor, Dept. of EEE Teaching and Research Dhaka University of Engineering & Technology (DUET), Gazipur
April 19, 2000 ~ March 31, 2003 Lecturer, Dept. of EEE Teaching and Research Dhaka University of Engineering & Technology (DUET), Gazipur
Type Title
Patents
  • M. A. Abedin, T. Koide H. J. Mattausch and Y. Tanaka, “Associative Memory and Searching System Using the Same,” US Patent No. US 7957171 B2, Date of Patent 07.06.2011. (http://ip.com/pat/US7957171)
  • H. J. Mattausch, T. Koide, Y. Tanaka and M. A. Abedin, “Amplifier Circuit and Associative Memory,” US Patent No. US 7746678 B2, Date of Patent 29.06.2010. (http://ip.com/pat/US7746678)
  • M. A. Abedin, T. Koide H. J. Mattausch and Y. Tanaka, “Associative Memory and Searching System Using the Same,” Japanese Patent No. 2009-134810A, Published on 18.06.2009. (http://ip.com/pat/JP2009134810A)
  • H. J. Mattausch, T. Koide and M. A. Abedin, “Associative Memory Device for Retrieving Minimum Euclidean Distance,” Japanese Patent No. JP 2007-80375A, Published on 29.03.2007. (http://ip.com/pat/JP2007080375A)
Journal Publications
  • M. Y. Ali, M. A. Abedin, M. S. Hossain and E. S. Hossain, “Optimization of Monoclinic Cu2SnS3 (CTS) Thin Film Solar Cell Performances Through Numerical Analysis,” Chalcogenide Letters, Vol. 17, No. 2, pp. 85 – 98, February 2020.
  • M. A. Abedin and M. Alauddin, “Solar Powered Mobile Phone Charger for Farmers,” DUET Journal, vol. 5, Issue 2, December 2019. (Accepted)
  • M. A. Abedin “PLC Controlled Two Axis Automatic Solar Tracking System,” International journal of Radio, Space and Aerospace Engineering, vol. 2, Issue 1, pp. 1 – 20, April 2017.
  • S. M. M. Alam, M. A. Abedin, U. K. Das and M. A. Rahman, “Radiation Pattern Investigation of n Element Microstrip Patch Antenna Array,” DUET Journal, vol. 1, Issue 3, pp. 24 – 28, June 2012.
  • K. R. Islam, M. A. Abedin, M. Akter and R. Deb, “High Speed ECG Image Compression Using Modified SPIHT,” International Journal of Computer and Electrical Engineering (IJCEE), vol. 3, No. 3, pp. 398 – 402, June 2011. (ISSN – Online: 1793-8198; Print: 1793-8163)
  • M. A. Abedin, T. Koide and H. J. Mattausch, “Nearest Euclidean Distance Search Associative Memory for High-Speed Pattern Matching,” DUET Journal, vol. 1, Issue 2, pp. 31 – 34, June 2011.
  • A. Ahmadi, H. J. Mattausch, M. A. Abedin, M. Saeidi and T. Koide, “An Associative Memory-Based Learning Model with an Efficient Hardware Implementation in FPGA,” Elsevier Journal of Expert System with Applications, vol. 38, Issue 4, pp. 3499 – 3513, April 2011.
  • M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search,” Japanese Journal of Applied Physics (JJAP), Vol. 46, No. 4B, pp. 2231-2237, 2007.
  • M. A. Abedin, Y. Tanaka, A. Ahmadi, S. Sakakibara, T. Koide and H. J. Mattausch, “Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-A, No. 6, pp. 1240-1243, 2007.
  • M. A. Abedin and M. M. S. Hassan, “Base Transit Time Model of a Bipolar Junction Transistor Considering Kirk Effect,” Journal of The Institution of Engineers, Singapore, Vol. 45, Issue 5, pp. 48-61, 2005. (ISSN – 0377-7464)
  • M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of Uniformly Doped Base Bipolar Transistors Considering Kirk Effect,” Journal of The Institution of Engineers, Malaysia, Vol. 66, No. 3, pp. 42-46, 2005. (ISSN – 0538-0057).
Conference Proceedings
  • A. N. M. Hossain and M. A. Abedin, “Implementation of an XOR based 16-bit Carry Select Adder for Area, Delay and Power Minimization,” International Conference on Electrical, Computer Communication Engineering (ECCE 2019), 07-09 February 2019, Cox’s Bazar, Bangladesh.
  • B. R. Biswas, R. Das, M. A. Abedin and ABM. H. Rashid, “Development of Simulation Model of a Controlled Rectifier for Reactive Power Compensation,” International Conference on Electrical and Computer Engineering (ICECE 2018), 20-22 December 2018, Dhaka, Bangladesh.
  • J. Barua and M. A. Abedin, “Design and Implementation of a FPGA Based Closed Loop Speed Controller for DC Motor using PWM Technique” International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE 2018),22-24 November, 2018, Gazipur, Bangladesh.
  • M. A. Kabir and M. A. Abedin, “Design and Implementation of a Microcontroller Based Forced Air Egg Incubator” International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE 2018),22-24 November, 2018, Gazipur, Bangladesh.
  • R. Das, B. R. Biswas, ABM H. Rashid and M. A. Abedin, “A Novel Low Buffered Optimized Solid State Drive Controller,” 9th International Conference on Electrical and Computer Engineering (ICECE 2016),   pp. 234 – 237, 20-22 December 2016, Dhaka, Bangladesh.
    (DOI: 10.1109/ICECE.2016.7853899)
  • A. Mohammad, M. A. Abedin and M. Z. R. Khan, “Implementation of a Three Phase Inverter for BLDC Motor Drive,” 9th International Conference on Electrical and Computer Engineering (ICECE 2016), pp. 337 – 340, 20-22 December 2016, Dhaka, Bangladesh.
    (DOI: 10.1109/ICECE.2016.7853925)
  • A. Mohammad, M. A. Abedin and M. Z. R. Khan, “Microcontroller Based Control System for Electric Vehicle,” International Conference on Informatics, Electronics & Vision (ICIEV 2016), pp. 693-696, 13-14 May 2016, Dhaka, Bangladesh.
    (DOI: 10.1109/ICIEV.2016.7760090)
  • M. A. Abedin, T. Koide and H. J. Mattausch, “Fully Parallel Single and Two-stage Associative Memories for High Speed Pattern Matching,” 5th International Conference on Electrical and Computer Engineering (ICECE 2008), pp. 291 – 296, 20-22 December 2008, Dhaka, Bangladesh.
    DOI:10.1109/ICECE.2008.4769219)
  • M. A. Abedin, A. Ahmadi, T. Koide and H. J. Mattausch, “Fully Parallel Associative Memory with Human Memory Type Learning Model,” 10th International Conference on Computer and Information Technology (ICCIT 2007), pp. 73 – 79, 27-29 December 2007, Dhaka, Bangladesh.
    (DOI: 10.1109/ICCITECHN.2007.4579361)
  • M. A. Abedin, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch, “Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories,” The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 32 – 37, 15-16 October 2007, Hokkaido, Japan.
  • Y. Tanaka, M. A. Abedin, S. Sakakibara, T. Koide and H. J. Mattausch, “A Fast Differential-Amplifier-Based Winner-Search Circuit for Fully Parallel Associative Memories,” The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 38 – 41, 15-16 October 2007, Hokkaido, Japan.
  • S. Sakakibara, M. A. Abedin, Y. Tanaka, H. J. Mattausch and T. Koide, “Associative memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept,” The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 21–25, 15-16 October 2007, Hokkaido, Japan.
  • M. A. Abedin, A. Ahmadi, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch, “Application of Fully Parallel Associative Memory in Two-Stage Pattern Matching,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 124 – 125, 29-30 January 2007, Tokyo, Japan.
  • H. J. Mattausch, T. Koide, M. A. Abedin and K Johguchi, “Functional-Memory Architectures for Information-Processing Systems,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 46 – 49, 29-30 January 2007, Tokyo, Japan.
  • A. Ahmadi, M. A. Abedin, H. J. Mattausch, T. Koide, Y. Shirakawa and A. Ritonga, “A Human-memory Based Learning Model and Hardware Prototyping in FPGA,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 120 – 123,       29-30 January 2007, Tokyo, Japan.
  • A. Ahmadi, H. J. Mattausch, M. A. Abedin, T. Koide, Y. Shirakawa and A. Ritonga, “Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory,” IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP 2007), pp. 214 – 219, 1-5 April 2007, Hawaii, USA.
  • Y. Tanaka , M. A. Abedin, T. Koide and H. J. Mattausch, “Mixed Analog-Digital Fully- Parallel Associative Memory with Differential Amplifier,” Technical Report of IEICE, Vol. 106, No. 548, pp. 31 – 36, 7-9 March 2007, Okinawa, Japan. (in Japanese)
  • M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006), pp. 1311 – 1314, 4-7 December 2006, Singapore.
  • M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Nearest-Euclidean-Distance Search Associative Memory with Fully Parallel Mixed Digital-Analog Match Circuitry,” Extended abstract of the Int. Conf. on Solid State Devices and Materials (SSDM’2006), pp. 282 – 283, 12-15 September 2006, Pacific Yokohama, Japan.
  • M. A. Abedin, T. Koide and H. J. Mattausch, “Fully-Parallel Nearest Euclidean Distance Search Associative Memory Architecture,” International PhD Student Workshop on SOC (IPS’2006), pp. 75 – 78, 24-28 July 2006, Taipei, Taiwan.
  • A. Ahmadi, M. A. Ritonga, M. A. Abedin, H. J. Mattausch and T. Koide, “A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA,” IEEE World Congress on Computational Intelligence (WCCI’2006), pp. 2702 – 2708, 16-21 July 2006, Vancouver, BC, Canada.
  • M. A. Abedin, K. Kamimura, A. Ahmadi, T. Koide, and H. J. Mattausch, “Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability,” The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2006), pp. 350 – 354, 3-4 April 2006, Nagoya, Japan.
  • A. Ahmadi, M. A. Abedin, H. J. Mattausch, and T. Koide, “A Parallel Hardware Design for Parametric Active Contour Models,” IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS 2005), pp. 609 – 613, 15-16 September 2005, Como, Italy.
  • M. A. Abedin, K. Kamimura, A. Ahmadi, H. J. Mattausch, and T. Koide, “Fully-Parallel Associative Memory Architecture Realizing Minimum Euclidean Distance Search,” 4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 58 – 59, 16th September 2005, Hiroshima, Japan.
  • A. Ahmadi, M. A. Abedin, K. Kamimura, Y. Shirakawa, K. Takemura, H. J.  Mattausch, and T. Koide, “Associative Memory Based Hardware Design for an OCR System and Prototyping with FPGA,” 4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 56 – 57, 16th September 2005, Hiroshima, Japan.
  • A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide, “An LSI hardware design for online character recognition using associative memory,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2005), pp. 464 – 467, 7-10 August 2005, Ohio, USA.
  • A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide, “Real-Time Character Recognition System Using Associative Memory Based Hardware,” 3rd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 40 – 41, 6th December 2004, Hiroshima, Japan.
  • M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of a Bipolar Junction Transistor Considering Kirk Effect,” International Conference on Electrical and Computer Engineering (ICECE), pp. 136 – 139, 26-28 December 2002, Dhaka, Bangladesh.
  • M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of Uniformly Doped Base Bipolar Transistors Considering Kirk Effect,” International Conference on Electrical Engineering (ICEE), pp. 93 – 100, 23-24 October 2002, Khulna, Bangladesh.
  • M. S. Rahman, M. N. Ahsan and M. A. Abedin, “Modified UDP for Reliable Data Transmission Through a Lossy Communication Link,” International Conference on Electrical Engineering (ICEE), pp. 191 – 196, 23-24 Oct 2002, Khulna, Bangladesh.
Topic Info
Supervisions
  • Philosophical Doctorate (Ph.D):  
  • Post-Graduate Supervision (Completed): 06 students
  • Undergraduate Supervision:  Currently 105 students.
Additional Charge
  • Controller of Examinations, Dhaka University of Engineering & Technology (DUET), Gazipur
    From July 06, 2018 to Present
  • Director, Institutional Quality Assurance Cell, Dhaka University of Engineering & Technology (DUET), Gazipur
    From April 27, 2015 to October 12, 2015
  • Dean, Faculty of Electrical & Electronic Engineering, Dhaka University of Engineering & Technology (DUET), Gazipur
    From April 13, 2013 to April 12, 2015
  • Head, Department of Electrical & Electronic Engineering, Dhaka University of Engineering & Technology (DUET), Gazipur
    From April 12, 2013 to April 11, 2015
  • Director, Computer Center, Dhaka University of Engineering & Technology (DUET), Gazipur
    From June 01, 2010 to April 25, 2013
  • Chairman, PABX Committee, Dhaka University of Engineering & Technology (DUET), Gazipur
    From July 11, 2010 to April 25, 2013
  • Provost, Dr. Kudrat-E-Khuda Hall, Dhaka University of Engineering & Technology (DUET), Gazipur
    From November 01, 2010 to October 31, 2012
Award
  • Session Excellent Presentation Award for the paper titled “Fully-Parallel Nearest Euclidean Distance Search Associative Memory Architecture,” in International PhD Student Workshop on SOC (IPS’2006), 24-28 July 2006, Taipei, Taiwan.