Personal Information of Professor Dr. Md. Anwarul Abedin

Name

Dr. Md. Anwarul Abedin

Designation

Professor

Department

EEE

Office Address

Building: Old Academic Building
Room # 2xx
PABX Ext.: 3027

 

Contact Information

Email at duet.ac.bd: Abedin at duet.ac.bd
Alternate Email: abedin14 at yahoo.com
Mobile: 01712070009
Fax: 02-9204709

Educational Qualifications

Degree University Country Year Field
Post-Doctoral BUET Bangladesh 2015-2017 VLSI
Ph.D. Hiroshima University Japan 2007 VLSI
M.Sc. BUET Bangladesh 2002 Solid State Electronics
B.Sc. BUET Bangladesh 1999 Electrical & Electronics

Field of Specialization:

Solid State Electronics, Mixed Digital-Analog VLSI

Research Interest:

Solid State Electronics, Mixed Digital-Analog VLSI , Industrial Electronics, PLC

Career Profile
(Job Profile)

Professor, From April 16, 2012 to date
Associate professor, From April 15, 2010 to April 15, 2012
Assistant Professor, From April 01, 2003 to April 14, 2010
Lecturer, From April 19, 2000 to March 31, 2003

Additional Charge List
(Present Designation and Offices)

Director
Institutional Quality Assurance Cell, DUET, Gazipur
From April 27, 2015 to October 12, 2015
Dean
Faculty of Electrical & Electronic Engineering, DUET, Gazipur
From April 13, 2013 to April 12, 2015
Head
Department of Electrical & Electronic Engineering, DUET, Gazipur
From April 12, 2013 to April 11, 2015
Director, Computer Center, DUET, Gazipur
From June 01, 2010 to April 25, 2013
Chairman, PABX Committee, DUET, Gazipur
From July 11, 2010 to April 25, 2013
Provost, Dr. Kudrat-E-Khuda Hall, DUET, Gazipur
From November 01, 2010 to October 31, 2012

Courses Taught
(Course Code and Title only)

Undergraduate Level:
EEE-1103: Electrical Circuit-I
EEE-2301: Electrical Machines-I
EEE-2501: Electronics-I
EEE-3701: Electrical & Electronic Measurement
EEE-4701: Control System
EEE-4705: VLSI Circuits
EEE-4907: High Voltage Engineering
Postgraduate Level:
EEE-6609: Digital Integrated Circuit Design
EEE-6705: MOS Devices
EEE-6706: Optoelectronic Devices

Thesis Supervision
(Number of Students)

M.Sc.: 05
B.Sc.: 105

Publication List (IEEE format)
(Year-wise publication List)

Journal:
2012:
1. S. M. M. Alam, M. A. Abedin, U. K. Das and M. A. Rahman, “Radiation Pattern Investigation of n Element Microstrip Patch Antenna Array,” DUET Journal, vol. 1, Issue 3, pp. 24 – 28, June 2012.
2011:
2. K. R. Islam, M. A. Abedin, M. Akter and R. Deb, “High Speed ECG Image Compression Using Modified SPIHT,” International Journal of Computer and Electrical Engineering (IJCEE), vol. 3, No. 3, pp. 398 – 402, June 2011. (ISSN – Online: 1793-8198; Print:1793-8163)3. M. A. Abedin, T. Koide and H. J. Mattausch, “Nearest Euclidean Distance Search Associative Memory for High-Speed Pattern Matching,” DUET Journal, vol. 1, Issue 2, pp. 31 – 34, June 2011.

4. A. Ahmadi, H. J. Mattausch, M. A. Abedin, M. Saeidi and T. Koide, “An Associative Memory-Based Learning Model with an Efficient Hardware Implementation in FPGA,”Elsevier Journal of Expert System with Applications, vol. 38, Issue 4, pp. 3499 – 3513, April 2011. (ISSN – 0957-4174, Impact Factor – 2.203 in 2011).

2007:
5. M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search,” Japanese Journal of Applied Physics (JJAP), Vol. 46, No. 4B, pp. 2231-2237, 2007. (ISSN – Online: 1347-4065 / Print: 0021-4922, Impact Factor – 1.058 in 2011).

6. M. A. Abedin, Y. Tanaka, A. Ahmadi, S. Sakakibara, T. Koide and H. J. Mattausch, “Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-A, No. 6, pp. 1240-1243, 2007. (ISSN – Online ISSN : 1745-1337, Impact Factor – 0.226 in 2011).

2005:
7. M. A. Abedin and M. M. S. Hassan, “Base Transit Time Model of A Bipolar Junction Transistor Considering Kirk Effect,” Journal of The Institution of Engineers, Singapore, Vol. 45, Issue 5, pp. 48-61, 2005. (ISSN – 0377-7464)

8. M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of Uniformly Doped Base Bipolar Transistors Considering Kirk Effect,” Journal of The Institution of Engineers, Malaysia, Vol. 66,     No. 3, pp. 42-46, 2005. (ISSN – 0538-0057).Conferences:
1.  M. A. Abedin, T. Koide and H. J. Mattausch, “Fully Parallel Single and Two-stage Associative Memories for High Speed Pattern Matching,” 5th International Conference on Electrical and Computer Engineering (ICECE 2008), pp. 291 – 296, 20-22 December 2008, Dhaka, Bangladesh.

2.  M. A. Abedin, A. Ahmadi, T. Koide and H. J. Mattausch, “Fully Parallel Associative Memory with Human Memory Type Learning Model,” 10th International Conference on Computer and Information Technology (ICCIT 2007), pp. 73 – 79, 27-29 December 2007, Dhaka, Bangladesh.

3.  M. A. Abedin, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch, “Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories,” The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007),      pp. 32 – 37, 15-16 October 2007, Hokkaido, Japan.

4.  Y. Tanaka, M. A. Abedin, S. Sakakibara, T. Koide and H. J. Mattausch, “A Fast Differential-Amplifier-Based Winner-Search Circuit for Fully Parallel Associative Memories,”The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007),   pp. 38 – 41, 15-16 October 2007, Hokkaido, Japan.

5.  S. Sakakibara, M. A. Abedin, Y. Tanaka, H. J. Mattausch and T. Koide, “Associative memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept,” The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 21–25, 15-16 October 2007, Hokkaido, Japan.

6.  M. A. Abedin, A. Ahmadi, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch, “Application of Fully Parallel Associative Memory in Two-Stage Pattern Matching,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 124 – 125,       29-30 January 2007, Tokyo, Japan.

7.  H. J. Mattausch, T. Koide, M. A. Abedin and K Johguchi, “Functional-Memory Architectures for Information-Processing Systems,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 46 – 49, 29-30 January 2007, Tokyo, Japan.

8. A. Ahmadi, M. A. Abedin, H. J. Mattausch, T. Koide, Y. Shirakawa and A. Ritonga, “A Human-memory Based Learning Model and Hardware Prototyping in FPGA,” 5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 120 – 123,       29-30 January 2007, Tokyo, Japan.

9.  A. Ahmadi, H. J. Mattausch, M. A. Abedin, T. Koide, Y. Shirakawa and A. Ritonga, “Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory,” IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP 2007), pp. 214 – 219, 1-5 April 2007, Hawaii, USA.

10. Y. Tanaka , M. A. Abedin, T. Koide and H. J. Mattausch, “Mixed Analog-Digital Fully- Parallel Associative Memory with Differential Amplifier,” Technical Report of IEICE, Vol. 106, No. 548, pp. 31 – 36, 7-9 March 2007, Okinawa, Japan. (in Japanese)

11. M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006), pp. 1311 – 1314, 4-7 December 2006, Singapore.

12. M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch, “Nearest-Euclidean-Distance Search Associative Memory with Fully Parallel Mixed Digital-Analog Match Circuitry,” Extended abstract of the Int. Conf. on Solid State Devices and Materials (SSDM’2006), pp. 282 – 283, 12-15 September 2006, Pacific Yokohama, Japan.

13. M. A. Abedin, T. Koide and H. J. Mattausch, “Fully-Parallel Nearest Euclidean Distance Search Associative Memory Architecture,” International PhD Student Workshop on SOC (IPS’2006), pp. 75 – 78, 24-28 July 2006, Taipei, Taiwan.

14.  A. Ahmadi, M. A. Ritonga, M. A. Abedin, H. J. Mattausch and T. Koide, “A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA,” IEEE World Congress on Computational Intelligence (WCCI’2006), pp. 2702 – 2708, 16-21 July 2006, Vancouver, BC, Canada.

15.  M. A. Abedin, K. Kamimura, A. Ahmadi, T. Koide, and H. J. Mattausch, “Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability,”The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2006),     pp. 350 – 354, 3-4 April 2006, Nagoya, Japan.

16. A. Ahmadi, M. A. Abedin, H. J. Mattausch, and T. Koide, “A Parallel Hardware Design for Parametric Active Contour Models,” IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS 2005), pp. 609 – 613, 15-16 September 2005, Como, Italy.

17.  M. A. Abedin, K. Kamimura, A. Ahmadi, H. J. Mattausch, and T. Koide, “Fully-Parallel Associative Memory Architecture Realizing Minimum Euclidean Distance Search,” 4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing,   pp. 58 – 59, 16th September 2005, Hiroshima, Japan.

18.  A. Ahmadi, M. A. Abedin, K. Kamimura, Y. Shirakawa, K. Takemura, H. J.  Mattausch, and T. Koide, “Associative Memory Based Hardware Design for an OCR System and Prototyping with FPGA,” 4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 56 – 57, 16th September 2005, Hiroshima, Japan.

19.  A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide, “An LSI hardware design for online character recognition using associative memory,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2005), pp. 464 – 467, 7-10 August 2005, Ohio, USA.

20.  A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide, “Real-Time Character Recognition System Using Associative Memory Based Hardware,” 3rd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing,       pp. 40 – 41, 6th December 2004, Hiroshima, Japan.

21. M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of a Bipolar Junction Transistor Considering Kirk Effect,” International Conference on Electrical and Computer Engineering (ICECE), pp.136 – 139, 26-28 December 2002, Dhaka, Bangladesh.

22. M. A. Abedin and M. M. S. Hassan, “Analytical Base Transit Time Model of Uniformly Doped Base Bipolar Transistors Considering Kirk Effect,” International Conference on Electrical Engineering (ICEE), pp. 93 – 100, 23-24 October 2002, Khulna, Bangladesh.

23. M. S. Rahman, M. N. Ahsan and M. A. Abedin, “Modified UDP for Reliable Data Transmission Through a Lossy Communication Link,” International Conference on Electrical Engineering (ICEE), pp. 191 – 196, 23-24 Oct 2002, Khulna, Bangladesh.